The integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, the functional density has generally increased while feature size has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
In order to continually meet performance requirements, there has been a desire to replace some of the polysilicon gate electrodes of an integrated circuit with metal gate electrodes. One process of implementing metal gates is termed a “gate last” or “replacement gate” methodology. In such a process, a dummy (e.g., sacrificial) polysilicon gate is initially formed, various processes associated with the semiconductor device are performed, and the dummy gate is subsequently removed and replaced with a metal gate.
As feature size decreased, it may also be desired to provide shorter effective gate length of a field effect transistor (FET). The shorter gate length may increase the speed of the transistor. However, due to photolithography limitations, providing a shorter gate length for a smaller dimension feature sizes may be difficult to obtain. The characteristics and performance of semiconductor devices can be altered by changing the sizes (e.g., length) of the FETs used. For example, it may be desired to decrease the effective gate length of a device to increase the speed, decrease the current, and/or alter other parameters of the FET.